What are the elements of bus design

Elements of bus designs ‍are given below:

(i) Bus Types

(ii) Method of Arbitration

(iii) Timing

(iv) Bus Width

(v) Data Transfer Type

(vi) Block Data Transfer

(i) Bus Types:

(a) Dedicated:

A line is permanently assigned either to one function.

An example of functional dedication is the use of separate dedicated address and data line.

(b) Multiplexed

Using the same lines for multiple purposes.

Eg:- Address and data information may be transmitted over the same set of lines.

At the beginning of the data transfer the address is placed   on the bus and the address valid line is activated.

The address is then remove from the same bus line is used for data transfer. 

(c) Physical Dedication

The use of multiple buses, each of which connects to only a subset of modules.

(ii) Method of Arbitration: Determining who can use the bus at a particular time.

(a) Centralized: A single hardware device called the bus controller or arbiter allocate time on the bus. The device may be a separate or a part of a processor.

(b) Distributed: There is no centralized controllers. Each module contains assess control logic and the modules act together.

(iii) Timing:

(a) Synchronous Timing: Bus includes a clock line upon which a clock transmits a regular sequence of alternating 1’s and 0’s. A single 1-0 transition is referred to as a clock cycle or bus cycle. All other devices on the bus can read the clock line. All events start at the beginning of a clock cycle.

Synchronous Timing

 (b) Asynchronous Timing: The occurrence of one event on abuse follows and depends on the occurrence of a previous event. Harder to implement and text than synchronous timing.

Asynchronous Timing

(iv) Bus Width:

•             Data bus: Wider = Better performance
•      Address bus: Wider = More locations can be referenced

(v) Data Transfer Type:

• Read-Modify-Write: A read followed immediately by a write to the same address.
•  Read-After-Write: Consisting of a write followed immediately by a read from the same address (for error checking purposes).

(vi) Block Data Transfer: One address cycle followed by n data cycles.

• First data item to or from specified address.
•  Remaining data items to or from subsequent addresses.