The factors of a bus design are explained below__
Bus
Design
Bus
types Method of
Arbitration
(i)
Dedicated (i)
Centralized
(i)
Multiplexed (ii) Distributed
Timing Bus width
(i)
Synchronous (i) Address
(ii)
Asynchronous (ii) Data
Data Transfer Type:
(i) Read
(ii) Write
(iii) Read- modify – write
(iv) Read- after write
(v) Block
Bus Types: Bus lines can be separated into two
generic types__
(i)
Dedicated
(ii)
Multiplexed
A dedicated bus line is permanently assigned either
to one function or to a physical subset of computer components.
Method of using the same liners for multiple
purposes is known as time multiplexing.
Method of Arbitration: In all but the simplest
systems, more than one module my need control of the bus. For example, an I/O
module.
The methods of arbitration are __
(i)
Centralized
(ii)
Distributed
Centralized:
In a centralized scheme, a single hardware device, referred to as a bus
controller or arbiter is responsible for allocating time on the bus.
Distributed:
In distributed scheme, there is no central controller; rather, each module
contains access control logic and the modules act together to share the bus.
Timing: Timing refers to the way in which events are
co-ordinate on the bus. Buses use either_
(i)
Synchronous timing.
(ii)
Asynchronous timing
Synchronous timing:
With synchronous timing, the occurrence of events on the bus is determined by a
clock.
Asynchronous timing:
With asynchronous timing the occurrence of one event on a bus follows and
depends on the occurrence of a previous event.
Bus width:
We have already addressed the concept of bus width. The width of the data bus
has an impact on system performance. The wider the data bus, the greater the
number of bits transferred at one time.
Data transfer type:
All buses support both write (master to slave) and read (slave to master)
transfers. A read – modify-write operation is simply a read followed
immediately by a right to the same address.
Read-after-write is an individual operation
consisting of a right followed it immediately by a read from the same address.
Some bus system also suffered a block data transfer.
In this case, one address cycle is followed by in data cycles.
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