Draw and explain the high performance bus structure

high performance bus structure

In fig-shows a typical realization of approach. Again there is a local bus that connects the processor to a cache controller. Whiz is in turn connected to a system bus that supports main memory. The cache controller is integrated into a bridge or buffering device that connects to the high speed bus. This bus supports connections to high-speed LANs, such as Fast Ethernet at 100 Mbps video and graphics workstation controllers, as well as interface controllers to local peripheral buss including SCSI and fire wire. The latter is a high speed bus arrangement specifically I/O devices. Lower speed devices are still supported off an expansion bus, with an interface buffering traffic between the expansion bus and the high-speed bus.

The advantage of this arrangement is that the high speed bus brings high demand devices into closer integration with the processor and at the same time is independent of the processor. Changes in processor architecture do not affect the high speed bus and vice-versa.